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| MC26LS30 Dual Differential (EIA-422-A)/ Quad Single-Ended (EIA-423-A) Line Drivers The MC26LS30 is a low power Schottky set of line drivers which can be configured as two differential drivers which comply with EIA-422-A standards, or as four single-ended drivers which comply with EIA-423-A standards. A mode select pin and appropriate choice of power supplies determine the mode. Each driver can source and sink currents in excess of 50 mA. In the differential mode (EIA-422-A), the drivers can be used up to 10 Mbaud. A disable pin for each driver permits setting the outputs into a high impedance mode within a +10 V common mode range. In the single-ended mode (EIA-423-A), each driver has a slew rate control pin which permits setting the slew rate of the output signal so as to comply with EIA-423-A and FCC requirements and to reduce crosstalk. When operated from symmetrical supplies (+5.0 V), the outputs exhibit zero imbalance The MC26LS30 is available in a 16-pin surface mount package. Operating temperature range is -40 to +85C. http://onsemi.com MARKING DIAGRAM 16 16 1 SO-16 D SUFFIX CASE 751B 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week MC26LS30D AWLYWW PIN CONNECTIONS VCC 1 Input A 2 Input B/ 3 Enable AB Mode 4 Gnd Input C/ Enable CD Input D VEE 5 6 7 8 (Top View) 16 SR-A 15 Output A 14 Output B 13 SR-B 12 SR-C 11 Output C 10 Output D 9 SR-D * Operates as Two Differential EIA-422-A Drivers, or Four * * * * * * * Single-Ended EIA-423-A Drivers High Impedance Outputs in Differential Mode Short Circuit Current Limit In Both Source and Sink Modes 10 V Common Mode Range on High Impedance Outputs 15 V Range on Inputs Low Current PNP Inputs Compatible with TTL, CMOS, and MOS Outputs Individual Output Slew Rate Control in Single-Ended Mode Replacement for the AMD AM26LS30 and National Semiconductor DS3691 Representative Block Diagrams Single-Ended Mode EIA-423-A SR-A Input A Out A SR-B Input B Out B SR-C Input C Out C SR-D Input D Out D ORDERING INFORMATION Device MC26LS30D MC26LS30DR2 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel Differential Mode EIA-422-A Enable AB Input A Out A Out B Out C Out D Input D Enable CD VCC-1 VEE-8 Gnd-5 Mode-4 (c) Semiconductor Components Industries, LLC, 2000 1 July, 2000 - Rev. 1 Publication Order Number: MC26LS30/D MC26LS30 MAXIMUM OPERATING CONDITIONS (Pin numbers refer to SO-16 package only.) Rating Power Supply Voltage Input Voltage (All Inputs) Applied Output Voltage when in High Impedance Mode (VCC = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1) Output Voltage with VCC, VEE = 0 V Output Current Junction Temperature Symbol VCC VEE Vin Vza Vzb IO TJ Value -0.5, +7.0 -7.0, +0.5 -0.5, +20 15 15 Self limiting -65, +150 - C Unit Vdc Vdc Vdc Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides conditions for actual device operation. RECOMMENDED OPERATING CONDITIONS Rating Power Supply Voltage (Differential Mode) Power Supply Voltage (Single-Ended Mode) Input Voltage (All Inputs) Applied Output Voltage (when in High Impedance Mode) Applied Output Voltage, VCC = 0 Output Current Operating Ambient Temperature (See text) All limits are not necessarily functional concurrently. Symbol VCC VEE VCC VEE Vin Vza Vzb IO TA Min +4.75 -0.5 +4.75 -5.25 0 -10 -10 -65 -40 Typ 5.0 0 +5.0 -5.0 - - - - - Max +5.25 +0.3 +5.25 -4.75 +15 +10 +10 +65 +85 Unit Vdc Vdc mA C http://onsemi.com 2 MC26LS30 ELECTRICAL CHARACTERISTICS (EIA-422-A differential mode, Pin 4 p 0.8 V, -40C tTA t 85C, 4.75 V p VCC p 5.25 V, VEE = Gnd, unless otherwise noted. Pin numbers refer to SO-16 package only.) Characteristic Output Voltage (see Figure 1) Differential, RL = , VCC = 5.25 V Differential, RL = 100 , VCC = 4.75 V Change in Differential Voltage, RL = 100 (Note 4.) Offset Voltage, RL = 100 Change in Offset Voltage*, RL = 100 Output Current (each output) Power Off Leakage, VCC = 0, -10 V p VO p +10 V High Impedance Mode, VCC = 5.25 V, -10 V p VO p +10 V Short Circuit Current (Note 2.) High Output Shorted to Pin 5 (TA = 25C) High Output Shorted to Pin 5 (-40C t TA t+85C) Low Output Shorted to +6.0 V (TA = 25C) Low Output Shorted to +6.0 V (-40C t TA t +85C) Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 p Vin p 15 V, VCC = 0 Clamp Voltage (Iin = -12 mA) Power Supply Current (VCC = +5.25 V, Outputs Open) (0 p Enable p VCC) Symbol VOD1 VOD2 VOD2 VOS VOS IOLK IOZ ISC- ISC- ISC+ ISC+ VIL VIH IIH IIHH IIL IIX VIK ICC - 16 30 Min - 2.0 - - - -100 -100 -150 -150 60 50 - 2.0 - - -200 - -1.5 Typ 4.2 2.6 10 2.5 10 0 0 -95 - 75 - - - 0 0 -8.0 0 - Max 6.0 - 400 3.0 400 +100 +100 -60 -50 150 150 0.8 - 40 100 - - - Unit Vdc Vdc mVdc Vdc mVdc A mA Vdc Vdc A Vdc mA TIMING CHARACTERISTICS (EIA-422-A differential mode, Pin 4 p 0.8 V, TA = 25C, VCC = 5.0 V, VEE = Gnd, (Notes 1. and 3.) unless otherwise noted.) Characteristic Differential Output Rise Time (Figure 3) Differential Output Fall Time (Figure 3) Propagation Delay Time - Input to Differential Output Input Low to High (Figure 3) Input High to Low (Figure 3) Skew Timing (Figure 3) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package Enable Timing (Figure 4) Enable to Active High Differential Output Enable to Active Low Differential Output Enable to 3-State Output From Active High Enable to 3-State Output From Active Low 1. 2. 3. 4. 5. Symbol tr tf tPDH tPDL tSK1 tSK2 tSK3 tPZH tPZL tPHZ tPLZ Min - - - - - - - - - - - Typ 70 70 90 90 9.0 2.0 2.0 150 190 80 110 Max 200 200 200 200 ns - - - ns 300 350 350 300 Unit ns ns ns All voltages measured with respect to Pin 5. Only one output shorted at a time, for not more than 1 second. Typical values established at +25C, VCC = +5.0 V, VEE = -5.0 V. Vin switched from 0.8 to 2.0 V. Imbalance is the difference between VO2 with Vin t 0.8 V and VO2 with Vin u 2.0 V. http://onsemi.com 3 MC26LS30 ELECTRICAL CHARACTERISTICS (EIA-423-A single-ended mode, Pin 4 q 2.0 V, -40C t TA t 85C, 4.75 V p VCC, |VEE p 5.25 V, (Notes 1. and 3.) unless otherwise noted). Characteristic Output Voltage (VCC = VEE = 4.75 V) Single-Ended Voltage, RL = (Figure 2) Single-Ended Voltage, RL = 450 , (Figure 2) Voltage Imbalance (Note 5.), RL = 450 Slew Control Current (Pins 16, 13, 12, 9) Output Current (Each Output) Power Off Leakage, VCC = VEE = 0, -6.0 V p VO p +6.0 V Short Circuit Current (Output Short to Ground, Note 2.) Vin p 0.8 V (TA = 25C) Vin p 0.8 V (-40C t TA t +85C) Vin w 2.0 V (TA = 25C) Vin w 2.0 V (-40C t TA t +85C) Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 p Vin p 15 V, VCC = 0 Clamp Voltage (Iin = -12 mA) Power Supply Current (Outputs Open) VCC = +5.25 V, VEE = -5.25 V, Vin = 0.4 V Symbol VO1 VO2 VO2 ISLEW IOLK ISC+ ISC+ ISC- ISC- VIL VIH IIH IIHH IIL IIX VIK ICC IEE Min 4.0 3.6 - - -100 60 50 -150 -150 - 2.0 - - -200 - -1.5 - -22 Typ 4.2 3.95 0.05 120 0 80 - -95 - - - 0 0 -8.0 0 - 17 -8.0 Max 6.0 6.0 0.4 - +100 150 150 -60 -50 0.8 - 40 100 - - - 30 - A A mA Unit Vdc Vdc Vdc A Vdc mA TIMING CHARACTERISTICS (EIA-423-A single-ended mode, Pin 4 q 2.0 V, TA = 25C, VCC = 5.0 V, VEE = -5.0 V, (Notes 1. and 3.) unless otherwise noted.) Characteristic Output Timing (Figure 5) Output Rise Time, CC = 0 Output Fall Time, CC = 0 Output Rise Time, CC = 50 pF Output Fall Time, CC = 50 pF Rise Time Coefficient (Figure 16) Propagation Delay Time, Input to Single Ended Output (Figure 5) Input Low to High, CC = 0 Input High to Low, CC = 0 Skew Timing, CC = 0 (Figure 5) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package 1. 2. 3. 4. 5. Symbol tr tf tr tf Crt tPDH tPDL tSK4 tSK5 tSK6 Min - - - - - - - - - - Typ 65 65 3.0 3.0 0.06 100 100 15 2.0 5.0 Max 300 300 - - - 300 300 ns - - - Unit ns s s/pF ns All voltages measured with respect to Pin 5. Only one output shorted at a time, for not more than 1 second. Typical values established at +25C, VCC = +5.0 V, VEE = -5.0 V. Vin switched from 0.8 to 2.0 V. Imbalance is the difference between VO2 with Vin t 0.8 V and VO2 with Vin u 2.0 V. http://onsemi.com 4 MC26LS30 Table 1 Inputs Operation Differential (EIA 422 A) (EIA-422-A) VCC +5.0 VEE Gnd Mode 0 0 0 0 0 0 1 1 1 1 1 X A 0 1 X 1 0 1 0 1 0 0 0 X B 0 0 1 0 0 0 0 0 1 0 0 X C 0 0 0 0 0 1 0 0 0 1 0 X D 0 1 1 0 1 X 0 0 0 0 1 X A 0 1 Z 1 0 1 0 1 0 0 0 Z Outputs B 1 0 Z 0 1 0 0 0 1 0 0 Z C 1 0 0 1 0 Z 0 0 0 1 0 Z D 0 1 1 0 1 Z 0 0 0 0 1 Z S ge Single-Ended ded (EIA 423 A) (EIA-423-A) +5.0 50 -5.0 50 X X = Don't Care Z = High Impedance (Off) 0 X VCC Vin (0.8 or 2.0 V) Mode = 0 RL/2 VOD2 RL/2 VOS Mode = 1 Vin (0.8 or 2.0 V) VCC RL VEE CL VO Figure 1. Differential Output Test Figure 2. Single-Ended Output Test VCC Vin Vin 100 500 pF VOD 1.5 V tPDH +3.0 V 1.5 V tPDL 0V S.G. 90% 50% Vout 10% tr tf 90% 50% 10% NOTES: 1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns. 2. tSK1 = tPDH-tPDL for each driver. 3. tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package. 4. tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package. Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay http://onsemi.com 5 MC26LS30 +3.0 V Vin VSS (Vin = Hi) Output Current (Vin = Lo) NOTES: 1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns. 2. Above tests conducted by monitoring output current levels. 1.5 V tPHZ 0.1 VSS/RL tPZH VSS/RL 0.5 VSS/RL 1.5 V 0V VCC 0 or 3.0 V En 500 pF 450 RL Vin S.G. tPLZ 0.1 VSS/RL VSS/RL tPZL 0.5 VSS/RL Figure 4. Differential Mode Enable Timing VCC Vin CC 450 VEE S.G. 500 pF Vin +2.5 V 1.5 V tPDH 90% 50% 10% tf 1.5 V tPDL 0V VO Vout 90% 50% 10% tr NOTES: 1. S.G. set to: f p 100 kHz; duty cycle = 50%; tr, tf, p10 ns. 2. tSK4 = tPDH-tPDL for each driver. 3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package. 4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package. Figure 5. Single-Ended Mode Rise/Fall Time and Data Propagation Delay http://onsemi.com 6 MC26LS30 5.0 VOD , OUTPUT VOLTAGE (V) 4.0 3.0 2.0 1.0 0 Differential Mode Mode = 0, VCC = 5.0 V 0.8 or 2.0 V 0 10 IO V OD 20 30 40 IO, OUTPUT CURRENT (mA) 50 60 10 0 40 I B , BIAS CURRENT (mA) Differential Mode Mode = 0 Supply Current = Bias Current + Load Current 30 20 VCC = 5.25 V 20 40 60 80 TOTAL LOAD CURRENT (mA) 100 120 Figure 6. Differential Output Voltage versus Load Current +100 I SC, SHORT CIRCUIT CURRENT (mA) Iin INPUT CURRENT mA) +60 +20 -20 -60 +5.0 0 -5.0 -10 -15 -20 -25 -1.0 1.0 VCC = 0 Figure 7. Internal Bias Current versus Load Current Normally Low Output VCC = 5.0 V Normally High Output Differential Mode Mode = 0, VCC = 5.0 V 0 1.0 2.0 3.0 4.0 Vza, APPLIED OUTPUT VOLTAGE (V) 5.0 6.0 Pins 2 to 4, 6, 7 -5.0 V t VEE t 0 Differential or Single-Ended Mode -100 3.0 5.0 7.0 9.0 11 13 15 Vin, INPUT VOLTAGE (V) (Pin numbers refer to SO-16 package only.) Figure 8. Short Circuit Current versus Output Voltage 4.5 VOH , OUTPUT VOLTAGE (V) VOL, OUTPUT VOLTAGE (V) -3.25 Figure 9. Input Current versus Input Voltage 4.0 -3.75 3.5 Single-Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V Vin = 1 0 -10 -20 -30 -40 IOH, OUTPUT CURRENT (mA) -50 -60 -4.25 Single-Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V Vin = 0 0 10 20 30 40 IOL, OUTPUT CURRENT (mA) 50 60 3.0 -4.75 Figure 10. Output Voltage versus Output Source Current Figure 11. Output Voltage versus Output Sink Current http://onsemi.com 7 MC26LS30 26 I B+ , BIAS CURRENT (mA) 0 I B- , BIAS CURRENT (mA) -5.0 22 Single Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V Supply Current = Bias Current + IOH 18 -10 Vin = Lo Vin = Hi Single-Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V Supply Current = Bias Current + IOL 160 80 0 -80 -160 IOL IOH TOTAL LOAD CURRENT (mA) -240 14 Vin = Lo Vin = Hi 10 240 160 80 0 -80 -160 -240 -15 IOL IOH TOTAL LOAD CURRENT (mA) -20 240 Figure 12. Internal Positive Bias Current versus Load Current Figure 13. Internal Negative Bias Current versus Load Current 100 I SC , SHORT CIRCUIT CURRENT (mA) 60 20 -20 -60 Single-Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V -4.0 0 -2.0 2.0 Vza, APPLIED OUTPUT VOLTAGE (V) 4.0 6.0 I SC + (mA) 110 90 70 50 I SC - (mA) -90 -100 -110 -40 -20 0 20 40 60 TA, AMBIENT TEMPERATURE (C) 85 Normally Low Output Normally Low Output Single or Differential Mode VCC = 5.0 V, VEE = -5.0 V or Gnd Normally High Output Normally High Output to Ground -100 -6.0 Figure 14. Short Circuit Current versus Output Voltage Figure 15. Short Circuit Current versus Temperature 1.0 k t r , t f , RISE/FALL TIME ( s) Single-Ended Mode Mode = 1 VCC = 5.0 V, VEE = -5.0 V 100 10 1.0 10 100 1.0 k CC, CAPACITANCE (pF) 10 k Figure 16. Rise/Fall Time versus Capacitance http://onsemi.com 8 MC26LS30 APPLICATIONS INFORMATION (Pin numbers refer to SO-16 package only.) Description The MC26LS30 is a dual function line driver - it can be configured as two differential output drivers which comply with EIA-422-A Standard, or as four single-ended drivers which comply with EIA-423-A Standard. The mode of operation is selected with the Mode pin (Pin 4) and appropriate power supplies (see Table 1). Each of the four outputs is capable of sourcing and sinking 60 to 70 mA while providing sufficient voltage to ensure proper data transmission. As differential drivers, data rates to 10 Mbaud can be transmitted over a twisted pair for a distance determined by the cable characteristics. EIA-422-A Standard provides guidelines for cable length versus data rate. The advantage of a differential (balanced) system over a single-ended system is greater noise immunity, common mode rejection, and higher data rates. Where extraneous noise sources are not a problem, the MC26LS30 may be configured as four single-ended drivers transmitting data rates to 100 Kbaud. Crosstalk among wires within a cable is controlled by the use of the slew rate control pins on the MC26LS30. Mode Selection (Differential Mode) of Figure 10 will vary directly with VCC, and the graph of Figure 11 will vary directly with VEE. A "high" output can only source current, while a "low" output can only sink current (except short circuit current - see Figure 14). The outputs will be in a high impedance mode only if VCC p 1.1 V. Changing VEE to 0 V does not set the outputs to a high impedance mode. Leakage current over a common mode range of 10 V is typically less than 1.0 A. The outputs have short circuit current limiting, typically less than 100 mA over a voltage range of 6.0 V (see Figure 14). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Capacitors connected between Pins 9, 12, 13, and 16 and their respective outputs will provide slew rate limiting of the output transition. Figure 16 indicates the required capacitor value to obtain a desired rise or fall time (measured between the 10% and 90% points). The positive and negative transition times will be within 5% of each other. Each output may be set to a different slew rate if desired. Inputs In this mode (Pins 4 and 8 at ground), only a +5.0 V supply 5% is required at VCC. Pins 2 and 7 are the driver inputs, while Pins 10, 11, 14 and 15 are the outputs (see Block Diagram on page 1). The two outputs of a driver are always complementary and the differential voltage available at each pair of outputs is shown in Figure 6 for VCC = 5.0 V. The differential output voltage will vary directly with VCC. A "high" output can only source current, while a "low" output can only sink current (except for short circuit current - see Figure 8). The two outputs will be in a high impedance mode when the respective Enable input (Pin 3 or 6) is high, or if VCC p 1.1 V. Output leakage current over a common mode range of 10 V is typically less than 1.0 A. The outputs have short circuit current limiting, typically, less than 100 mA over a voltage range of 0 to +6.0 V (see Figure 8). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Pins 9, 12, 13 and 16 are not normally used when in this mode, and should be left open. (Single-Ended Mode) The five inputs determine the state of the outputs in accordance with Table 1. All inputs (regardless of the operating mode) have a nominal threshold of +1.3 V, and their voltage must be kept within a range of 0 V to +15 V for proper operation. If an input is taken more than 0.3 V below ground, excessive currents will flow, and the proper operation of the drivers will be affected. An open pin is equivalent to a logic high, but good design practices dictate that inputs should never be left open. Unused inputs should be connected to ground. The characteristics of the inputs are shown in Figure 9. VCC requires +5.0 V, 5%, regardless of the mode of operation. The supply current is determined by the IC's internal bias requirements and the total load current. The internally required current is a function of the load current and is shown in Figure 7 for the differential mode. In the single-ended mode, VEE must be -5.0 V, 5% in order to comply with EIA-423-A standards. Figures 12 and 13 indicate the internally required bias currents as a function of total load current (the sum of the four output loads). The discontinuity at 0 load current exists due to a change in bias current when the inputs are switched. The supply currents vary 2.0 mA as VCC and VEE are varied from 4.75 V to 5.25 V. Sequencing of the supplies during power-up/ power-down is not required. Bypass capacitors (0.1 F minimum on each supply pin) are recommended to ensure proper operation. Capacitors reduce noise induced onto the supply lines by the switching action of the drivers, particularly where long P.C. board tracks are involved. Additionally, the capacitors help absorb Power Supplies In this mode (Pin 4 2.0 V) VCC requires +5.0 V, and VEE requires -5.0 V, both 5.0%. Pins 2, 3, 6, and 7 are inputs for the four drivers, and Pins 15, 14, 11, and 10 (respectively) are the outputs. The four drivers are independent of each other, and each output will be at a positive or a negative voltage depending on its input state, the load current, and the supply voltage. Figures 10 & 11 indicate the high and low output voltages for VCC = 5.0 V, and VEE = -5.0 V. The graph http://onsemi.com 9 MC26LS30 transients induced onto the drivers' outputs from the external cable (from ESD, motor noise, nearby computers, etc.). Operating Temperature Range The maximum ambient operating temperature, listed as +85C, is actually a function of the system use (i.e., specifically how many drivers within a package are used) and at what current levels they are operating. The maximum power which may be dissipated within the package is determined by: PDmax + TJmax * TA RqJA The junction temperature calculates to: TJ + 85C ) (0.454 W SOIC package. 120C W) + 139C for the Since the maximum allowable junction temperature is not exceeded in any of the above cases, either package can be used in this application. 2) Single-Ended Mode Power Dissipation For the single-ended mode, the power dissipated within the package is calculated from: PD + (IB) VCC) ) (IB* VEE) ) [ (IO (VCC * VOH) ] (each driver) where RJA = package thermal resistance which is typically: 120C/W for the SOIC (D) package, TJmax = max. allowable junction temperature (150C) TA = ambient air temperature near the IC package. 1) Differential Mode Power Dissipation For the differential mode, the power dissipated within the package is calculated from: PD + [ (VCC * VOD) IO ] (each driver) ) (VCC IB) where: VCC = the supply voltage VOD = is taken from Figure 6 for the known value of IO IB = the internal bias current (Figure 7) As indicated in the equation, the first term (in brackets) must be calculated and summed for each of the two drivers, while the last term is common to the entire package. Note that the term (VCC -VOD) is constant for a given value of IO and does not vary with VCC. For an application involving the following conditions: TA = +85C, IO = -60 mA (each driver), VCC = 5.25 V, the suitability of the package types is calculated as follows. The power dissipated is: PD + [ 3.0 V 60 mA PD + 454 mW 2 ] ) (5.25 V 18 mA) The above equation assumes IO has the same magnitude for both output states, and makes use of the fact that the absolute value of the graphs of Figures 10 and 11 are nearly identical. IB+ and IB- are obtained from the right half of Figures 12 and 13, and (VCC - VOH) can be obtained from Figure 10. Note that the term (VCC - VOH) is constant for a given value of IO and does not vary with VCC. For an application involving the following conditions: TA = +85C, IO = -60 mA (each driver), VCC = 5.25 V, VEE = -5.25 V, the suitability of the package types is calculated as follows. The power dissipated is: PD + (24 mA 5.25 V) ) (*3.0 mA [ 60 mA 1.45 V 4.0 ] PD + 490 mW *5.25 V) ) The junction temperature calculates to: TJ + 85C ) (0.490 W SOIC package. 120C W) + 144C for the Since the maximum allowable junction temperature is not exceeded in any of the above cases, either package can be used in this application. http://onsemi.com 10 MC26LS30 SYSTEM EXAMPLES (Pin numbers refer to SO-16 package only.) Differential System An example of a typical EIA-422-A system is shown in Figure 17. Although EIA-422-A does not specifically address multiple driver situations, the MC26LS30 can be used in this manner since the outputs can be put into a high impedance mode. It is, however, the system designer's responsibility to ensure the Enable pins are properly controlled so as to prevent two drivers on the same cable from being "on" at the same time. The limit on the number of receivers and drivers which may be connected on one system is determined by the input current of each receiver, the maximum leakage current of each "off" driver, and the DC current through each terminating resistor. The sum of these currents must not exceed the capability of the "on" driver (60 mA). If the cable is of any significant length, with receivers at various points along its length, the common mode voltage may vary along its length, and this parameter must be considered when calculating the maximum driver current. The cable requirements are defined not only by the AC characteristics and the data rate, but also by the DC resistance. The maximum resistance must be such that the minimum voltage across any receiver inputs is never less than 200 mV. The ground terminals of each driver and receiver in Figure 17 must be connected together by a dedicated wire (or the shield) in the cable to provide a common reference. Chassis grounds or power line grounds should not be relied on for this common connection as they may generate significant common mode differences. Additionally, they usually do not provide a sufficiently low impedance at the frequencies of interest. Single-Ended System minimum voltage across any receiver inputs is never less than 200 mV. The ground terminals of each driver and receiver in Figure 18 must be connected together by a dedicated wire (or the shield) in the cable so as to provide a common reference. Chassis grounds or power line grounds should not be relied on for this common connection as they may generate significant common mode differences. Additionally, they usually do not provide a sufficiently low impedance at the frequencies of interest. Additional Modes of Operation If compliance with EIA-422-A or EIA-423-A Standard is not required in a particular application, the MC26LS30 can be operated in two other modes. 1) The device may be operated in the differential mode (Pin 4 = 0) with VEE connected to any voltage between ground and -5.25 V. Outputs in the low state will be referenced to VEE, resulting in a differential output voltage greater than that shown in Figure 6. The Enable pins will operate the same as previously described. 2) The device may be operated in the single-ended mode (Pin 4 = 1) with VEE connected to any voltage between ground and -5.25 V. Outputs in the high state will be at a voltage as shown in Figure 10, while outputs in a low state will be referenced to VEE. Termination Resistors An example of a typical EIA-423-A system is shown in Figure 18. Multiple drivers on a single data line are not possible since the drivers cannot be put into a high impedance mode. Although each driver is shown connected to a single receiver, multiple receivers can be driven from a single driver as long as the total load current of the receivers and the terminating resistor does not exceed the capability of the driver (60 mA). If the cable is of any significant length, with receivers at various points along its length, the common mode voltage may vary along its length, and this parameter must be considered when calculating the maximum driver current. The cable requirements are defined not only by the AC characteristics and the data rate, but also by the DC resistance. The maximum resistance must be such that the Transmission line theory states that, in order to preserve the shape and integrity of a waveform traveling along a cable, the cable must be terminated in an impedance equal to its characteristic impedance. In a system such as that depicted in Figure 17, in which data can travel in both directions, both physical ends of the cable must be terminated. Stubs leading to each receiver and driver should be as short as possible. In a system such as that depicted in Figure 18, in which data normally travels in one direction only, a terminator is theoretically required only at the receiving end of the cable. However, if the cable is in a location where noise spikes of several volts can be induced onto it, then a terminator (preferably a series resistor) should be placed at the driver end to prevent damage to the driver. Leaving off the terminations will generally result in reflections which can have amplitudes of several volts above VCC or several volts below ground or VEE. These overshoots/undershoots can disrupt the driver and/or receiver, create false data, and in some cases, damage components on the bus. http://onsemi.com 11 MC26LS30 En R En TTL D RT En TTL D TTL R TTL R TTL TTL D En TTL D R En TTL D RT En TTL TTL R D TTL Twisted Pair NOTES: 1. Terminating resistors RT should be located at the physical ends of the cable. 2. Stubs should be as short as possible. 3. Receivers = AM26LS32, MC3486, SN75173 or SN75175. 4. Circuit grounds must be connected together through a dedicated wire. Figure 17. EIA-422-A Example CC TTL D RT + R - TTL CC TTL D RT + R - TTL CC TTL D RT + R - TTL CC TTL D RT + R - TTL MC26LS30 AM26LS32, MC3486, SN75173, or SN75175 Figure 18. EIA-423-A Example http://onsemi.com 12 MC26LS30 PACKAGE DIMENSIONS SO-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 13 MC26LS30 Notes http://onsemi.com 14 MC26LS30 Notes http://onsemi.com 15 MC26LS30 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (Mon-Fri 2:30pm to 7:00pm CET) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (Mon-Fri 2:00pm to 7:00pm CET) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (Mon-Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 16 MC26LS30/D |
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